Maharshi Sanand Yadav T

🚀 New GVIM Tutorial is Live!

Still editing files line by line? There's a much faster way!

In this tutorial, you'll learn how to add text to the beginning of every line in GVIM and Notepad++ using powerful editing techniques. This is a huge time-saver for VLSI engineers, software developers, Linux users, and anyone working with large text files.

🎥 Watch now: https://youtu.be/MudgV8uZALA

If you found this tutorial helpful:
👍 Like the video
💬 Leave a comment with your favorite GVIM trick
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Happy coding! 🚀

1 week ago | [YT] | 1

Maharshi Sanand Yadav T

🔒 Members Exclusive

🎥 Watch the Video:
https://youtu.be/WTP6yb7pako
This week's tutorial covers one of the most frequently asked STA interview topics:

📌 Reg-to-Out Timing Path
📌 In-to-Reg Timing Path
📌 Setup Analysis
📌 set_input_delay & set_output_delay

🎁 Member Challenge:

If FF0 → Logic A → Output Port is analyzed at block level, what is the endpoint of the timing path?

Reply with your answer in the comments. I'll review and respond personally.


📚 Standard Cell Characterization Playlist:
youtube.com/playlist?list=PLS...

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youtube.com/@maharshisanandyadav

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Thank you for helping build our VLSI learning community.


– T Maharshi Sanand Yadav

1 month ago (edited) | [YT] | 5

Maharshi Sanand Yadav T

🚀 Max Load / Max Capacitance Explained in the Simplest Way!

In this video, we clearly explain Max Load (Maximum Capacitance) in Standard Cell Characterization.

Topics Covered:
• What is Max Load?
• Importance in Liberty (.lib)
• Step-by-step Max Cap calculation
• Impact on Synthesis and STA

This video is useful for:
Standard Cell Characterization | Cadence Liberate | SiliconSmart | Synthesis | STA | Timing Analysis

🎥 Watch now: https://youtu.be/aRHWcJ4vHKU

📚 Join Channel Membership for full VLSI courses & exclusive content:
youtube.com/@maharshisanandyadav/join

#MaxLoad #MaxCap #VLSI #StandardCell #Characterization #STA #Synthesis #ASIC #Semiconductor #Timing #Liberate #SiliconSmart #TMSYTutorials

Tags: max load, max capacitance, standard cell characterization, liberty file max cap, vlsi timing basics, cadence liberate tutorial, silicon smart characterization, sta constraints, synthesis constraints, max load calculation, vlsi tutorial, max cap lib

4 months ago | [YT] | 0

Maharshi Sanand Yadav T

🚀 Max Transition / Max Slew Calculation Explained Simply!

In this video, we explain Max Transition (Max Slew) in Standard Cell Characterization.

Topics Covered:
• What is Max Transition?
• Importance in Liberty (.lib)
• How to calculate max slew
• Impact on Synthesis and STA

Perfect for engineers working in:
Standard Cell Characterization | Synthesis | STA | Timing Analysis

🎥 Watch now: https://youtu.be/lFx-aRbIFOo

📚 Join Channel Membership for full VLSI courses & exclusive content:
youtube.com/@maharshisanandyadav/join

#MaxTransition #MaxSlew #VLSI #StandardCell #Characterization #STA #Synthesis #ASIC #Semiconductor #Timing #Liberate #SiliconSmart #TMSYTutorials

Tags: max transition, max slew, standard cell characterization, liberty file, vlsi timing, sta basics, synthesis constraints, cadence liberate, silicon smart, vlsi tutorial, timing analysis, max_transition lib

4 months ago | [YT] | 0

Maharshi Sanand Yadav T

NLDM vs CCS | Delay Arcs, Unateness & Combinational Timing

Understanding delay arcs and unateness is critical for mastering STA.

In this video:
• CCS current-based timing vs NLDM delay tables
• Combinational pin-pair relationships
• Positive, Negative & Non-Unate arc behavior
• Practical .lib structure comparison

▶️ Watch here:
👉 https://youtu.be/87poURsTnfE

💎 Become a Channel Member:
👉 youtube.com/maharshisanandyadav/join

#STA #VLSI #NLDM #CCS #TimingAnalysis #StandardCellCharacterization #EDA

5 months ago | [YT] | 1

Maharshi Sanand Yadav T

Delay Arc in Standard Cell Characterization | NLDM Explained

Delay arcs define how timing flows through a cell — without them, STA doesn’t exist.

In this video, you’ll understand:
• Pin-to-pin timing dependency
• Driver, net & receiver modeling
• How NLDM timing tables are built
• How STA tools consume delay arcs

▶️ Watch here:
👉 https://youtu.be/cuDQeUYiOBs

💎 Become a Channel Member:
👉 youtube.com/maharshisanandyadav/join

#DelayArc #STA #VLSI #TimingLibrary #StandardCellCharacterization #EDA

5 months ago | [YT] | 0

Maharshi Sanand Yadav T

Input Pin Capacitance Explained | NLDM vs CCS

Input capacitance is NOT just a number — it’s a timing accuracy driver 🚀

In this video, you’ll learn:
• NLDM vs CCS input capacitance modeling
• Receiver capacitance tables
• Role of input slew & output load
• Why CCS is essential for deep-submicron nodes

▶️ Watch here:
👉 https://youtu.be/MAQYVv49j8E

💎 Become a Channel Member:
👉 youtube.com/maharshisanandyadav/join

#STA #VLSI #TimingModels #CCS #NLDM #StandardCellCharacterization #ASIC #EDA

5 months ago | [YT] | 0

Maharshi Sanand Yadav T

Input Pin Capacitance – One Concept, Big Impact 🔥

Most timing issues start with misunderstanding input pin capacitance.

In this video, you’ll learn:
✅ What input pin capacitance is
✅ Estimation vs Empirical vs Numerical methods
✅ How tools calculate it
✅ How it is written in the Liberty file

📺 Watch now:
👉 https://youtu.be/RPZ0dYw3coQ

🔐 Support the channel & get exclusive VLSI content
👉 Join here: youtube.com/maharshisanandyadav/join

#VLSI #StandardCellCharacterization #STA #TimingClosure #Liberty #EDA

5 months ago | [YT] | 0

Maharshi Sanand Yadav T

📊 CCS vs ECSM – Output Waveforms Explained

• CCS models output current waveform
• ECSM models output voltage waveform
• Used for advanced timing & noise accuracy

🎥 Watch here 👇
https://youtu.be/vjkNXv_xYxU

⭐ Support the channel & unlock exclusive VLSI content
👉 Join Membership:
🔗 youtube.com/maharshisanandyadav/join

#VLSI #StandardCell #CCS #ECSM #LibraryCharacterization #EDA

5 months ago | [YT] | 0